User`s guide

Tar get Preferences
ADC
The int
ernal timing of the ADC module is controlled by the
high-s
peed peripheral clock (HSPCLK). The A DC operating clock
speed
is derived in several prescaler stages from the HSPCLK
speed
. For more information about configuring these scalers, refer
to “Co
nfiguring ADC Parameters for Acquisition Window Width”
in the
Target Support Package TC2 documentation (available if
you h
ave installed Target Support Package TC2).
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