User`s guide

F2812 eZdsp
3-40
• DSP Chip
- DSP Chip Label — DSP chip model. Select the DSP chip installed on your
target. The chip model is fixed for the F2812 eZdsp. If you change the chip
model, an error will be generated in code generation.
-
eCAN — Parameters that affect the extended control area network
(eCAN) module. Most of these parameters affect the eCAN bit timing. The
CAN protocol divides the nominal bit time into four segments, which are
reflected in the settable parameters below. The four segments are
SYNCSEG — Time used to synchronize the nodes on the bus. It is always
one time quantum (TQ), which is defined as
where SYSCLK is the CAN module system clock frequency, and the
BitRatePrescaler is defined below.
PROP_SEG — Time used to compensate for the physical delays in the
network
PHASE_SEG1 — Phase used to compensate for positive edge phase error
PHASE_SEG2 — Phase used to compensate for negative edge phase error
The settable parameters are
BitRatePrescaler — Value by which to scale the bit rate. Valid values are
from 1 to 256. As noted in the equation above, this value determines the
value of TQ.
EnhancedCANMode — Whether to use the CAN module in extended
mode, which provides additional mailboxes and time stamping. The
default is
True. Setting this parameter to False enables only standard
mode.
TQ
1
SYSCLK
--------------------------
BitRatePrescalar 1+()⋅=