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UG640 (v 12.2) July 23, 2010

Design Styles for the DSP48

About the DSP48

Xilinx Virtex® and Spartan® devices offer an efficient building block for DSP applications

called the DSP48 (also known as the Xtreme DSP Slice). The DSP48 is available as a System

Generator block which is a wrapper for the DSP48 UNISIM primitive. Architectural and

usage information for this primitive can be found in the DSP48 Users Guide for your

device.

The DSP48 combines an 18-bit by 18-bit signed multiplier with a 48-bit adder and a

programmable mux to select the adder's inputs. It implements the basic operation: "p=a*b

+(c+cin);", however other operations can be selected dynamically. Optional input and

multiplier pipeline registers are also included and must be used to achieve maximum

speed. Also included with the DSP48 are high performance local interconnects between

adjacent DSP48 blocks (BCIN-BCOUT and PCIN-PCOUT). The DSP48 also includes

support for symmetric rounding. This combination of features enables DSP systems which

use the higher-speedDSP48 devices to be clocked at over 500 MHz.

There are three ways to program a DSP48 in System Generator:

• Use Standard Components - Map designs to Mult and AddSub blocks or use higher-

level IP such as the MACFIR filter generator blocks. This approach is useful if the

design uses a lower-speed clock and the mapping to DSP48s is not required.

• Use Synthesizable Blocks - Structure the design to map onto the DSP48's internal

architecture and compose the design from synthesizable Mult, AddSub, Mux and

Delay blocks. This approach relies on logic synthesis to infer DSP48 blocks where

appropriate. This approach gives the compiler the most freedom and can often

achieve full-rate performance.

• Use DSP48 Blocks - Use System Generator's DSP48 and DSP48 Macro blocks to

directly implement DSP48-based designs. This is the highest performance design

technique. Be aware however that obtaining maximum performance and minimum

area for designs using DSP48s may require careful mapping of the target algorithm to

the DSP48's internal architecture, as well as the physical planning of the design.