User guide

System Generator for DSP User Guide www.xilinx.com 97
UG640 (v 12.2) July 23, 2010
Resetting Auto-Generated Clock Enable Logic
Table 1-1:
Block Name
Synchronized
to ce_clr
Synchronized to
ce after ce_clr
deasserted
( 1 sample cycle
delay)
Behavior after ce_clr is de-asserted
and the next ce pulse
Down Sampler
with Last Value
of frame
Yes N/A The last sampled value is held till the
new ce signal arrives.
Down Sampler
with First Value
of frame
No No Re-synchronization does not occur
after de-assertion of the ce_clr signal.
Up Sampler
with copy
samples
Yes N/A In hardware, this block is
implemented as a wire.
Up Sampler
with zeros
inserted
No Yes The last value (zero or sample) is held
till the next destination ce signal
arrives.
Time Division
Multiplexer
No Yes The TDM block samples through all
the remaining input channels and
then sets the output to 0 till the next ce
arrives. The new ce signal re-
synchronizes the output to the new
frame definition.
Time Division
Demultiplexer
No Yes The TDD block holds the output
channels to the same value till the
next ce signal arrives. The new ce
signal re-synchronizes the output to
the new frame definition.
Parallel to Serial No Yes The p2s block samples through all the
remaining data words and then holds
the output to the last sampled word
until the next ce arrives. The new ce
signal starts the conversion of the
parallel data stream to a serial one.
Serial to Parallel No Yes The s2p block holds the output when
the ce_clr is asserted. When de-
asserted, the input is sampled on the
last value of the input sample frame,
and the output occurs on the first ce
pulse corresponding to the output
rate.