User guide

80 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 1: Hardware Design Using System Generator
• The ce16_c4b7e244_group_to_ce16_cb47e244_group1 constraint is for all the
synchronous elements after the down sampler and it is set to sixteen, the system
sample period (3)
• The down sampling block in the SRAM design performs a down sample by 2. The
ce2_f488215c_group_to_ce2_f488215c_group2 constraint is for all the synchronous
elements after the down sampler and is set to twice the system sample period (4)
With the new integration between System Generator and Project Navigator, these
constraints are automatically associated and consolidated by Project Navigator up to the
top-level design. This flow is only available starting with Release 10.1.
Simulating the Entire Design
To perform a behavioral simulation of the top_level design, do the following:
1. System Generator creates VHDL files and invokes the selected logic synthesis tool to
generate the HDL Netlist. These VHDL files are used when simulating the top-level
design. The VHDL files generated for a design are named <design>_cw.vhd, and
<design>.vhd. Open the custom ModelSim do file named “top_level_testbench.do”
to see how the VHDL files for both designs are referenced.
Memory initialization (.mif) and coefficient (.coe) files that are used during
simulation must be placed in the same directory as the top-level VHDL file. For this
example, the mif files are copied from both hdl_netlist1 and hdl_netlist2 sub-
folders by the following statement in the ModelSim do file (top_level_testbench.do):
foreach i [glob ../hdl_netlist1/*.mif] {
file copy -force $i .
In a case where there are also coefficient files, you can add a similar statement to the do
file to copy the files up to the top-level VHDL file.
2. Change the Design View to Simulation. Select the top_level_testbench-
structural(top_level.vhd) source file. This file is imported into the project as a
testbench file, thus allowing you to simulate the design using the Simulator.