User guide

System Generator for DSP User Guide www.xilinx.com 45
UG640 (v 12.2) July 23, 2010
Automatic Code Generation
no testbench is requested, then the key files produced by System Generator are the
following:
If a testbench is requested, then, in addition to the above, System Generator produces files
that allow simulation results to be compared. The comparisons are between Simulink
simulation results and corresponding results from ModelSim. The additional files are the
following:
File Name or Type Description
<design>.vhd/.v This contains most of the HDL for the design
<design>_cw.vhd/.v This is a HDL wrapper for <design>_files.vhd/.v. It
drives clocks and clock enables.
.edn and .ngc files Besides writing HDL, System Generator runs CORE
Generator
™ (coregen) to implement portions of the design.
Coregen writes EDIF files whose names typically look
something like
multiplier_virtex2_6_0_83438798287b830b.edn.
Other required files may be supplied as .ngc files.
globals This file consists of key/value pairs that describe the design.
The file is organized as a Perl hash table so that the keys and
values can be made available to Pearl scripts using Perl evals.
<design>_cw.xcf (or .ncf) This contains timing and port location constraints. These are
used by the Xilinx synthesis tool XST and the Xilinx
implementation tools. If the synthesis tool is set to something
other than XST, then the suffix is changed to .ncf.
<design>_cw.ise This allows the HDL and EDIF to be brought into the Xilinx
project management tool Project Navigator.
hdlFiles This contains the full list of HDL files written by System
Generator. The files are listed in the usual HDL dependency
order.
synplify_<design>.prj, or
xst_<design>.pr
These files allow the design to be compiled by the synthesis
tool you specified.
vcom.do This script can be used in ModelSim to compile the HDL for a
behavioral simulation of the design.
File Name or Type Description
Various .dat files These contain the simulation results from Simulink.
<design>_tb.vhd/.v This is a testbench that wraps the design. When simulated in
ModelSim, this testbench compares simulation results from
Simulink against those produced by ModelSim.
vsim.do This script can be used in ModelSim to run a testbench
simulation.
pn_behavioral.do,
pn_postmap.do,
pn_postpar.do,
pn_posttranslate.do
These files allow various ModelSim simulations to be started
inside Project Navigator.