User guide

410 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
adding a block to a Configurable
Subsystem
86
and Configurable Subsystems 83
blocksets 21
defining a Configurable Subsystem
83
deleting a block from a Configurable
Subsystem
86
generating hardware from Config-
urable Subsystems
87
output files 44
processing a design with physical
design tools
90
resetting auto-generated Clock En-
able logic
96
system-level modeling 20
using a Configurable Subsystem 85
System Generator block
compiling and simulating
40
System Generator Constraints
constraints file
46
example 47
IOB timing and placement 46
multicycle path 46
system clock period 46
System Generator Design Flows
algorithm exploration
19
implementing a complete design 19
implementing part of a larger design
19
System-Level Modeling 20
T
Tapped Delay Lines 17
TDM data streams 16
Testbench
HDL
50
Time-Division Multiplexed 16
Timing Analysis
clock skew and jitter
390
concepts review 389
cross-probing 391
displaying low-level names 391
histogram charts 392, 395
improving failing paths 395
observing slow paths 390
path analysis example 389
period and slack 389
statistics 394
trace report 394
tutorial 397
Timing Analyzer
invoking on previously-generated
data
388
Timing and Clocking 24
Timing and Power Analysis
compilation type
Compiling for
timing and power
analysis
387
Trace Report
timing analysis
394
Tutorials
Black Box
Dynamic Black Boxes
361
Importing a Core Generator
Module
339
Importing a Core Generator
Module that Needs a VHDL
Wrapper
345
Importing a Verilog Module
360
Importing a VHDL Module 352
Importing, Simulating, and Ex-
porting an Encrypted VHDL
Module
370
Simulating Several Black Boxes
Simultaneously
363
ChipScope
Using ChipScope in System
Generator
130
Clocking
Using the Clock Genera-
tor(DCM) Option
28
Using the Expose Clock Ports
Option
33
Hardware/Software Co-Design
Creating a New XPS Project
186
Creating MicroBlaze Peripher-
als in System Generator
173
Designing and Simulating Mi-
croBlaze Processor Systems
178
Using PicoBlaze in System Gen-
erator
168
Timing Analysis
Using the Timing Analyzer
397
Using System Generator and SDK to
Co-Debug an Embedded DSP De-
sign
200
U
Underdevelopment
export pcore as
383
Using XFLOW 405
V
Variable Clock Frequency
selecting for Hardware Co-Sim
231
W
Wizards
Base System Builder
186
Black Box Configuration 323, 352
EDK Import 164
XPS Import 180
X
Xilinx
Blockset
22
Reference Blockset 22
Xilinx Tool Flow Settings
for HW Co-Sim
252
xlCallChipScopeAnalyzer 404
xlmax 51
xlSimpleArith 52
xltarget
defining new Compilation Targets
402
xlTimingAnalysis 388
xltools_postgeneration 403, 404
xltools_target 403
XPower
power analysis
387
XPS Import Wizard 180