User guide

System Generator for DSP User Guide www.xilinx.com 41
UG640 (v 12.2) July 23, 2010
Automatic Code Generation
Compilation Type and the Generate Button
Pressing the Generate button instructs System Generator to compile a portion of the
design into equivalent low-level results. The portion that is compiled is the sub-tree whose
root is the subsystem containing the block. (To compile the entire design, use a System
Generator block placed at the top of the design.) The compilation type (under
Compilation) specifies the type of result that should be produced. The possible types are
• Two types of Netlists, HDL Netlist and NGC Netlist
• Bitstream - produces an FPGA configuration bitstream that is ready to run in a
hardware FPGA platform
• EDK Export Tool - for exporting to the Xilinx Embedded Development Kit
• Various varieties of hardware co-simulation
• Timing and Power Analysis - a report on the timing and power consumption of the
design.
HDL Netlist is the type used most often. In this case, the result is a collection of HDL and
EDIF files, and a few auxiliary files that simplify downstream processing. The collection is
ready to be processed by a synthesis tool (e.g., XST), and then fed to the Xilinx physical
design tools (i.e., ngdbuild, map, par, and bitgen) to produce a configuration bitstream for
a Xilinx FPGA. The files that are produced are described in more detail in Compilation
Results.
NGC Netlist is similar to HDL Netlist but the resulting files are NGC files instead of HDL
files.
When the type is a variety of hardware co-simulation, then System Generator produces an
FPGA configuration bitstream that is ready to run in a hardware FPGA platform. The
particular platform depends on the variety chosen. For example, when the variety is
Hardware Co-simulation > XtremeDSP Development Kit > PCI and USB, then the
bitstream is suitable for the XtremeDSP board (available for separate purchase from
Xilinx). System Generator also produces a hardware co-simulation block to which the
bitstream is associated. This block is able to participate in Simulink simulations. It is
functionally equivalent to the portion of the design from which it was derived, but is
implemented by its bitstream. In a simulation, the block delivers the same results as those
produced by the portion, but the results are calculated in working hardware.
The remaining compilation parameters are described in the table below. Some are
available only when the compilation type is HDL Netlist. For example, the clock pin
location cannot be chosen for a hardware co-simulation compilation because it is fixed in
each hardware FPGA platform.
Control Description
Part Defines the FPGA part to be used.
Target Directory Defines where System Generator should write compilation results.
Because System Generator and the FPGA physical design tools
typically create many files, it is best to create a separate target
directory, i.e., a directory other than the directory containing your
Simulink model files. The directory can be an absolute path (e.g.
c:\netlist) or a path relative to the directory containing the model
(e.g. netlist).