User guide

System Generator for DSP User Guide www.xilinx.com 409
UG640 (v 12.2) July 23, 2010
Installing an SP601/SP605 Board for
Ethernet Hardware Co-Sim
299
Installing an SP601/SP605 Board for
JTAG Hardware Co-Sim
305
Introduction
to FPGAs
14
J
JTAG Hardware Co-Sim
board support package files
313
Detecting New Board Packages 319
installing board-support packages
318
manually specifying board-specific
ports
316
obtaining platform information 314
providing your own top-level 317
supporting new boards 307
JTAG-based HW Co-Sim 299, 301, 303,
305
L
Linux
Installing the Proxy Executable for
Linux Users
281
Locked pin
Hybrid DCM-CE Option
28
M
MATLAB
compiling into an FPGA
51
complex multiplier with latency 55
disp function 71
finite state machines 62
FIR example 66
optional input ports 60
parameterizable accumulator 63
passing parameters into the MCode
block
57
RPN calculator 69
simple arithmetic operation 52
simple selector 51
simple shift operation 56
Memory Map Creation
for processor integration
146
M-Function
black box configuration
324
MicroBlaze
in System Generator tutorial
173
System Design and Simulation 178
ML402 Board
Installation for JTAG HW Co-Sim
301
ML605 Board
Installation for JTAG HW Co-Sim
303
Modeling
bit-true and cycle-true
24
Multiple Clock Applications 118
Multirate Designs
color shading by signal rate
24
Multirate Models 25
N
Netlisting
multiple clock designs
121
Network-Based Ethernet Hardware Co-
Sim
239
NGC Netlist Compilation 378
Notes
for higher performance FPGA design
89
O
OutputFiles
produced by System Generator
44
Oversampling 26
P
Parameter Passing 37
Pcore
export as under development
383
pcore
exporting
166
exporting a System Generator model
as a peripheral
147
PicoBlaze
designing within System Generator
166
in System Generator tutorial 168
overview 166
PLB-based pcore 144
Point-to-Point Ethernet HW Co-Sim 235
Power Analysis
using XPower
387
Processor Integration
Hardware Co-Sim
147
hardware generation 147
memory map creation 146
using custom logic 144
Project Navigator
integration flow with System Gener-
ator
74
R
Rate-Changing Blocks 25
Real-Time Signal Processing
using Hardware Co-Sim
267
Reducing
Clock Enable Fannout
90
Reference Blockset
Xilinx
22
Reset pin
Hybrid DCM-CE Option
28
Resource Estimation 39
S
SBD Builder
saving plugin files
312
specifying board-specific I/O ports
310
SDK Standalone
Migrating a software project from
XPS
193
Shared Memory Support
for HW Co-Sim
242
Signal Types 23
displaying data types 23
full precision 23
gateway blocks 23
user-specified precision 23
Simulink System Period 43
Software Project
migrating from XPS to SDK
193
SP601/SP605 Board
Installation for Ethernet Hardware
C-Sim Co-Sim
299
Installation for JTAG Hardware Co-
Sim
305
Spartan-3A DSP 1800A Starter Board
Installation for Ethernet HW Co-Sim
293
Synchronization Mechanisms
indeterminate data
36
valid ports 36
Synchronous Clocking 26
Clock Enable option 27
Expose Clock Ports option 28
Hybrid DCM-CE option 27, 42
System Generator