User guide

408 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
DCM reset pin 42
Debugging
using ChipScope Pro
130
Defining New Compilation Targets 402
Target Info functions
xltools_target
403
the xltarget Function 402
Discrete Time Systems 24
Distinct Clocks
generating multiple cycle-true is-
lands
118
DSP48
design styles for
99
design techniques 106
mapping from the DSP48 block 101
mapping standard components to
100
mapping to from logic synthesis
tools
100
physical planning for 107
DSP48 Macro block 102
E
EDK
generating software drivers
148
support from System Generator 163
writing a software program 151
EDK Export Tool 383
exporting a pcore 166
EDK Import Wizard 164
EDK Processor
exposing processor ports
165
importing 163
Encrypted VHDL File
how to import as a Black Box
370
Ethernet-based HW Co-Sim 293
Export pcore
enable Custom Bus Interfaces
384
Exporting
a pcore
166
a System Generator model as a pcore
147
Expose Clock Ports Option
tutorial
33
F
Fanout Reduction
for Clock Enable
90
FDATool
using in digital filter applications
109
FPGA
a brief introduction
14
generating a bitstream 93
notes for higher performance 89
Frame-Based Acceleration
using Hardware Co-Sim
254
FSL-based pcore 144
Full Precision signal type 23
G
Generating
an FPGA bitstream
93
EDK software drivers 148
Generating an FPGA Bitstream
Generating an FPGA Bitstream
93
H
Hardware
oversampling
26
Hardware Co-Sim 225
blocks 228
choosing a compilation target 227
compiling shared memories 243
co-simulating lockable shared mem-
ories
246
co-simulating shared FIFOs 249
co-simulating shared registers 248
co-simulating unprotected shared
memories
245
Installing Software on the Host PC
277
Installing the Proxy Executable for
Linux Users
281
invoking the code generator 227
JTAG hardware requirements 307
Loading the Sysgen HW Co-Sim
Configuration Files
279
Network-Based Ethernet 239
Point-to-Point Ethernet 235
processor integration 147
restrictions on shared memories 252
selecting the target clock frequency
231
Setting Up the Local Area Network
on the PC
277
shared memory support 242
using for frame-based acceleration
254
using for real-time signal processing
267
Xilinx tool flow settings 252
Hardware Co-Simulation Compilation
387
Hardware Debugging
using ChipScope Pro
130
Hardware Generation 147
Hardware Generation Mode
EDK pcore
147
HDL netlist 147
Hardware/Software Co-Design 144
Examples
creating MicroBlaze Peripherals
in System Generator
173
designing and simulating Mi-
croBlaze Processor Systems
178
using EDK 186
using PicoBlase in System Gen-
erator
168
HDL Co-Sim
configuring the HDL simulator
335
co-simulating multiple black boxes
337
HDL Netlist Compilation 378
HDL Testbench 50
Hierarchical Controls 44
Histogram Charts
from Timing Analyzer
392, 395
Hybrid DCM-CE Option
locked pin
28
reset pin 28
tutorial 28
I
Implementing
a complete design
19
part of a design 19
Importing
a System Generator design
73
an EDK processor 163
an EDK project 147
Importing a System Generator Design 73
integration design rules 73
integration flow with Project Navi-
gator
74
step-by-step example 75
Installation
Installing a Spartan-3A DSP 1800A
Starter Board for Hardware Co-
Sim
293
Installing am ML402 Board for JTAG
Hardware Co-Sim
301
Installing an ML605 Board for JTAG
Hardware Co-Sim
303