User guide

System Generator for DSP User Guide www.xilinx.com 407
UG640 (v 12.2) July 23, 2010
A
Addressable Shift Register block 17
Algorithm Exploration 19
ASR block 17
Asynchronous Clocking 26
Auto-Generated Clock Enable Logic
resetting in System Generator
96
Automatic Code Generation 39
B
Bit-Accurate 21
Bitstream Compilation 379
Bit-True Modeling 24
Black Box
Configuration M-Function
adding new ports
326
black box API 331
black box clocking 329
combinational paths 330
configuring port sample rates
328
configuring port types 327
defining block ports 326
dynamic output ports 328
error checking 331
language selection 325
obtaining a port object 326
specifying the top-level entity
325
specifying Verilog parameters
330
specifying VHDL Generics 330
SysgenBlockDescriptor Mem-
ber Variables
331
SysgenBlockDescriptor meth-
ods
332
SysgenPortDescriptor Member
Variables
334
SysgenPortDescriptor methods
334
Examples 338
advanced black box example us-
ing ModelSim
365
dynamic black boxes 361
importing a Core Generator
module
339
importing a Core Generator
module that needs a VHDL
wrapper
345
importing a Verilog module
359
importing a VHDL module 352
importing a Xilinx Core Genera-
tor module
338
Importing an Encrypted VHDL
File
370
Importing, Simulating, and Ex-
porting an Encrypted VHDL
Module
370
simulating several black boxes
simultaneously
363
HDL Co-Sim
configuring the HDL simulator
335
co-simulating multiple black
boxes
337
Black Box Configuration
M-function
324
Black Box Configuration Wizard 323
Block Masks 37
Blockset
Xilinx
22
C
ChipScope Pro Analyzer 130
Clock Domain Partitioning 119
Clock Enable
Fanout Reduction
90
Clock Frequency
selecting for Hardware Co-Sim
231
Clocking
and timing
24
asynchronous 26
synchronous 26
Clocking Options
Clock Enable
27
Expose Clock Ports 28
Hybrid DCM-CE 27, 42
Code Generation
automatic
39
Color Shading
blocks by signal rate
24
Compilation Type
using XFLOW
405
Compilation Types
Bitstream Compilation
379
configuring and installing the Com-
pilation Target
404
creating new compilation targets
401
EDK Export Tool 383
Hardware Co-Simulation Compila-
tion
387
HDL Netlist Compilation 378
NGC Netlist Compilation 378
Compiling for
bitstream generation
379
EDK Export 383
Hardware Co-Simulation 387
NGC Netlist generation 378
Compiling for HDL Netlist generation
378
Compiling MATLAB
complex multiplier with latency
55
disp function 71
finite state machines 62
FIR example 66
into an FPGA 51
optional input ports 60
parameterizable accumulator 63
passing parameters into the MCode
block
57
RPN calculator 69
shift operation 56
simple arithmetic operation 52
simple selector 51
Compiling Shared Memories
for HW Co-Sim
243
Configurable Subsystems and System
Generator
83
Configuring and Installing the Compila-
tion Target
404
Constraints File
System Generator
46
Controls
hierarchical
44
Creating Compilation Targets 401
Crossing Clock Domains 120
Custom Bus Interfaces
for exported pcore
384
Cycle-Accurate 21
Cycle-True Clock Islands 118
Cycle-True Modeling 24
D
DCM locked pin 42
Index