User guide

System Generator for DSP User Guide www.xilinx.com 401
UG640 (v 12.2) July 23, 2010
Creating Compilation Targets
Excellent! No more failing paths! The design has been rescued, all in record time and
without using a more expensive part. Surely raises and promotions shall follow you for all
your days.
Note that all paths now have but a single level of logic. What exactly has happened here?
Let us examine the Synplify Pro schematic to see how the modified circuit was
synthesized:
See that there is an extra set of registers (highlighted in red) in between the two levels of
logic. The circuit functions the same as before but with an additional cycle of latency.
Use Retiming to Rescue the Design
If a cycle of latency had to be eliminated to match the latency of the original design, it
might be possible to remove the final output register or the input registers. This would
increase the constraints upon the paths outside the Xilinx chip (i.e., the copper paths on the
PCB), but it may be feasible depending upon board-level path delays. This would be an
example of retiming, because the latency is the same but the registers have been moved into
the logic "cloud".
Creating Compilation Targets
The HDL and netlist files that System Generator produces when it compiles a design into
hardware must be run through additional tools in order to produce a configuration
bitstream file that is suitable for your FPGA. A typical flow that allows you to generate an
FPGA configuration file is ProjectNavigator. There are other ways in which a bitstream can
be generated for your model. For example, it is possible to configure System Generator to
automatically run the tools necessary to produce a configuration file when it compiles a
design. This is advantageous since the complete bitstream generation process is
accomplished inside the tool. Moreover, you can have System Generator run different tools
(e.g., ChipScope™ Pro Analyzer and iMPACT) once the configuration file is generated for
a model.
The way in which System Generator compiles a model into hardware depends on the
compilation target that is chosen for the design. The HDL Netlist compilation target is
most common, and generates an HDL netlist of your design plus any cores that go along