User guide

400 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 5: System Generator Compilation Types
This will add a register to the end of the XOR gate. We will change the latency on blocks
xor_2a and xor_2b. We know from examining the Synplify Pro schematic that the
outputs of these blocks form the output of the first level of logic in the synthesized design.
The modified System Generator looks very similar with the exception of the z
-1
on the
labels of the two modified XOR blocks, indicating their new latency.
We generate this design as before and examine the slow paths: