User guide

40 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 1: Hardware Design Using System Generator
Compiling and Simulating Using the System Generator Block
System Generator automatically compiles designs into low-level representations. Designs
are compiled and simulated using the System Generator
block. This topic describes how to
use the block.
Before a System Generator design can be simulated or translated into hardware, the design
must include a System Generator block. When creating a new design, it is a good idea to
add a System Generator block immediately. The System Generator block is a member of
the Xilinx Blockset’s Basic Elements and Tools libraries. As with all Xilinx blocks, the
System Generator block can also be found in the Index library.
A design must contain at least one System Generator block, but can contain several System
Generator blocks on different levels (one per level). A System Generator block that is
underneath another in the hierarchy is a slave; one that is not a slave is a master. The scope
of a System Generator block consists of the level of hierarchy into which it is embedded
and all subsystems below that level. Certain parameters (e.g. Simulink System Period)
can be specified only in a master.
Once a System Generator block is added, it is possible to specify how code generation and
simulation should be handled. The block’s dialog box is shown below: