User guide

System Generator for DSP User Guide www.xilinx.com 397
UG640 (v 12.2) July 23, 2010
Timing and Power Analysis Compilation
Tutorial Example: Using the Timing Analyzer
Sometimes the hardware created by System Generator may not meet the requested timing
requirements. This is typically due to a setup time violation in the design. A setup time
violation means that a particular signal cannot get from the output of one synchronous
element to the input of another synchronous element within the requested clock period
and subject to the second synchronous element's setup time requirement.
Let us use an example to show how we would use the timing analyzer to improve circuit
performance. Our example will be a parity calculator that will find the parity of a byte by
using an 8-input XOR. The design can be found at:
<ISE_Design_Suite_tree>/sysgen/examples/timing_analysis/parity_tes
t.mdl
The design has eight one-bit gateway inputs that are registered by one-bit registers. These
are processed by seven 2-input XOR blocks. These have a latency of zero and thus are
purely combinational. The final register, parity_reg, registers the final result (the parity)
which is connected to an output gateway. The design appears to have three levels of logic,
because each path fanning in to parity_reg goes through three XOR blocks.