User guide

396 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 5: System Generator Compilation Types
f. Using Hard Cores. Are you using a ROM that is implemented in distributed RAM
when it would operate much faster in a block memory hard core? Do you have a
wide adder that would benefit from being put in a DSP48 block, which can operate
at 500MHz? Take advantage of the embedded hard cores.
g. New Paradigms. Do you need to create a large delay? Instead of using a counter
with a long carry chain, why not build a delay out of cascaded Johnson rings using
SRL16s? Or how about using an LFSR? Neither requires a carry chain and can
operate much faster. Sometimes you have to rethink certain design elements
completely.
2. Eliminate overconstraints. Ensure that elements of your design that only need to be
operated at a subsampled rate are designed that way by using the downsample and
upsample blocks in System Generator. If these blocks are not used, then the timing
analyzer is not aware that these sections of the circuit are subsampled, and the design
is overconstrainted.
3. Change the constraints. Is it possible to run the design at a lower clock speed? If so,
this is an easy way to meet your requirements. Unfortunately, this is rarely possible
due to design requirements.
4. Increase PAR effort levels. The mapper and place & route tools (PAR) in ISE take
effort levels as arguments. When using ISE (from the Project Navigator GUI), try the –
timing option in MAP. You may also increase the PAR effort levels which will increase
the PAR execution time but may also result in a faster design.
5. Multipass PAR using SmartXplorer. PAR is an iterative process and is somewhat
chaotic in that the initial conditions can vastly influence the final result. SmartXplorer
can be invoked from Project Navigator and allows you to run multiple implementation
flows using different sets of implementation properties designed to optimize design
performance.
6. Floorplanning. This step should be avoided if possible, but can yield huge
improvements. The automatic placer in PAR can be improved upon by human
intervention. Floorplanning places critical elements close to each other on the Xilinx
die, reducing net delays. The PACE tool in ISE may be used for CPLD. A more
advanced tool, PlanAhead™ software, is used for FPGA.
7. Use a faster part. This is often the first solution seized upon, but is also expensive. If
you are using an old Xilinx part, porting your design to a newer, faster Xilinx part may
often save money because the new parts may be cheaper on account of Moore's Law.
However, moving to a faster part in the same family incurs significant extra costs, and
often isn't necessary if the previous steps are followed.