User guide

354 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 4: Importing HDL Modules
Be aware of the following rules when working this example:
♦ A synchronous HDL design that is associated with a black box must have one or
more clock and clock enable ports. These ports must occur in pairs, one clock for
each clock enable, and vice-versa. Each of these ports must be of type std_logic.
The name of the clock port must contain the substring clk. The name of the clock
enable port must be the same as the name of the clock port, but with ce
substituted for clk.
♦ The clock enable port has a specific meaning to System Generator and is not a
general purpose user enable for the block. Refer to the topic Black Box HDL
Requirements and Restrictions for details.
6. Double click on the black box block. The dialog box shown below appears:
The following are the fields in the dialog box:
♦ Block configuration M-function - This specifies the name of the configuration M-
function for the black box. In this example, the field contains the name of the
function that was generated by the Configuration Wizard. By default, the black
box uses the function the wizard produces. You can, however, substitute one you
produce yourself. For more information on the configuration M-function, refer to
the topic Black Box Configuration M-Function.
♦ Simulation mode - There are three simulation modes:
- Inactive - When the mode is Inactive, the black box participates in the
simulation by ignoring its inputs and producing zeros. This setting is
typically used when a separate simulation model is available for the black
box, and the model is wired in parallel with the black box using a simulation
multiplexer. Black Box Tutorial Example 1: Importing a Core Generator
Module that Satisfies Black Box HDL Requirements shows how this is
accomplished.
-ISE Simulator - When the mode is ISE Simulator, simulation results for the
black box are produced using co-simulation on the HDL associated to the
black box.