User guide

350 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 4: Importing HDL Modules
9. Drag and drop the black box from the "Basic Elements" library in the
coregen_import_example2.mdl. Select fir_compiler_8tap_wrapper.vhd
for the top-level HDL file.
10. Connect the black box to the open wires.
11. Open the fir_compiler_8tap_wrapper_config.m file, and add the VHDL file,
EDIF netlist and MIF files to the black box file list as shown below. These files get
included as part of the System Generator netlist for the design when it is generated.
Note:
The order in which the files are added in the configuration function is the order in which they
get compiled during synthesis and simulation.