User guide

System Generator for DSP User Guide www.xilinx.com 349
UG640 (v 12.2) July 23, 2010
Black Box Examples
♦ Open the fir_compiler_8tap.vho file.
♦ Copy the component declaration from fir_compiler_8tap.vho and paste it
in fir_compiler_8tap_wrapper.vhd in the component declaration area.
(after -- Add Component Declaration from VHO file ------)
♦ Copy the core instantiation template from fir_compiler_8tap.vho and paste
it in fir_compiler_8tap_wrapper.vhd in the architecture body.
(after ------------- ADD INSTANTIATION Template -----)
♦ Copy the port declaration for the component fir_compiler_8tap and paste it
for the fir_compiler_8tap entity declaration
(after ---- Add Port declaration for entity ----)
♦ Add the ce port to the top-level entity declaration, and change the case of the CLK
port to clk.
8. Start Simulink and open the following design file:
<ISE_Design_Suite_tree>/sysgen/examples/coregen_import/example2
/coregen_import_example2.mdl