User guide

348 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 4: Importing HDL Modules
♦ This example will show you how to import a core that does not have a CE (clock
enable) port. As shown below, verify that the CE port option is not selected, then
click Generate..
4. CORE Generator produces the following files:
♦ fir_compiler_8tap.ngc: Implementation netlist
♦ fir_compiler_8tap.vhd: VHDL wrapper for behavioral simulation
♦ fir_compiler_8tap.vho: Core instantiation template
♦ fir_compiler_8tap.xco: Parameters selected for core generation
♦ Multiple .mif files: Memory initialization files for functional simulation
5. Since this core does not have a ce port and the System Generator blackbox requires a
clk, ce pair, you need to specify a core wrapper to add a ce port to the top level.
6. Open the following empty template wrapper file:
<ISE_Design_Suite_tree>/sysgen/examples/coregen_import/example2
/ fir_compiler_8tap_wrapper.vhd
This file contains an empty entity declaration.
7. Modify the template wrapper according to the instructions below: