User guide

346 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 4: Importing HDL Modules
3. Customize and generate the FIR Compiler 4.0 core with the following parameters:
♦ Component Name: fir_compiler_8tap
♦ Load Coefficients: fir_compiler_8tap.coe file located in sysgen directory
♦ Input Sampling Frequency: 25
♦ Clock Frequency: 300
♦ Leave the other parameters set to the default values
♦ Click Next >