User guide

342 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 4: Importing HDL Modules
4. Click Generate. Core Generator produces the following files after generation:
♦ cordic_sincos.ngc: Implementation netlist
♦ cordic_sincos.vhd: VHDL wrapper for behavioral simulation
♦ cordic_sincos.vho: Core instantiation template
♦ cordic_sincos.xco: Parameters selected for core generation
5. Start Simulink and open the design file
(<ISE_Design_Suite_tree>/sysgen/examples/coregen_import/example
1/coregen_import_example1.mdl)
6. Drag and drop the black box from the Xilinx "Basic Elements" library into the model
coregen_import_example1.mdl. Select cordic_sincos.vhd for the top-level
HDL file and click Open.
7. Connect the input and output ports of the black box to the open wires.