User guide

334 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 4: Importing HDL Modules
SysgenPortDescriptor Member Variables
SysgenPortDescriptor Methods
Type Member Description
String name Tells the name of the port.
Integer simulinkPortNumber Tells the index of this port in Simulink.
Indexing starts with 1 (as in Simulink).
Boolean typeKnown True if this port's type is known, and
false otherwise.
String type Type of the port, e.g., UFix_<n>_<b>,
Fix_<n>_<b>, or Bool
Boolean isBool True if port type is Bool, and false
otherwise.
Boolean isSigned True if type is signed, and false
otherwise.
Boolean isConstant True if port is constant, and false
otherwise.
Integer width Tells the port width.
Integer binpt Tells the binary point position, which
must be an integer in the range
0..width.
Boolean rateKnown True if the rate is known, and false
otherwise.
Double rate Tells the port sample time. Rates are
positive integers expressed as MATLAB
doubles. A rate can also be infinity,
indicating that the port outputs a
constant.
Method Description
setName(name) Sets the HDL name to be used for this port.
setSimulinkPortNumber(num) Sets the index associated with this port in Simulink.
num tells the index to assign. Indexing starts with 1
(as in Simulink).
setType(typeName) Sets the type of this port to type. Type must be one of
Bool, UFix_<n>_<b> , Fix_<n>_<b> , signed or
unsigned. The last two choices leave the width and
binary point position unchanged.
setWidth(w) Sets the width of this port to w.
setBinpt(bp) Sets the binary point position of this port to bp.
makeBool() Makes this port Boolean.
makeSigned() Makes this port signed.
makeUnsigned() Makes this port unsigned.