User guide

322 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 4: Importing HDL Modules
Black Box HDL Requirements and Restrictions
An HDL component associated with a black box must adhere to the following System
Generator requirements and restrictions:
• The entity name must not collide with any other entity name in the design.
• Bi-directional ports are supported in HDL black boxes, however they will not be
displayed in the System Generator as ports; they only appear in the generated HDL
after netlisting.
• For Verilog black boxes, the module and port names must be lower case and must
follow standard VHDL naming conventions.
• Any port that is a clock or clock enable must be of type std_logic. (For Verilog black
boxes, ports must be of non-vector inputs, e.g., input clk.)
• Clock and clock enable ports in black box HDL should be expressed as follows: Clock
and clock enables must appear as pairs (i.e., for every clock, there is a corresponding
clock enable, and vice-versa). Although a black box may have more than one clock
port, a single clock source is used to drive each clock port. Only the clock enable rates
differ.
• Each clock name (respectively, clock enable name) must contain the substring clk, for
example my_clk_1 and my_ce_1.
Black Box Tutorial Example 3:
Importing a VHDL Module
Describes how to use the Black Box block to import
VHDL into a System Generator design and how to use
ModelSim to co-simulate.
Black Box Tutorial Example 4:
Importing a Verilog Module
Demonstrates how Verilog black boxes can be used in
System Generator and co-simulated using ModelSim.
Black Box Tutorial Example 5:
Dynamic Black Boxes
Demonstrates dynamic black boxes using a transpose
FIR filter black box that dynamically adjusts to
changes in the widths of its inputs.
Black Box Tutorial Example 6:
Simulating Several Black Boxes
Simultaneously
Demonstrates how several System Generator Black
Box Blocks can be co-simulated simultaneously, using
only one ModelSim license while doing so.
Black Box Tutorial Exercise 7:
Advanced Black Box Example
Using ModelSim
Describes how to design a Black Box block with a
dynamic port interface and how to configure a black
box using mask parameters. Also, describes how to
assign generic values based on input port data types
and how to save black box blocks in Simulink libraries
for later reuse. How to specify custom scripts for
ModelSim HDL co-simulation is also covered.
Black Box Tutorial Example 8:
Importing, Simulating, and
Exporting an Encrypted VHDL
File
Describes how to import a design as an encrypted
VHDL file into a Black Box block, simulate the design,
then export the VHDL back out as a separate
encrypted file from the rest of the netlist.
Black Box Tutorial Exercise 9:
Prompting a User for Parameters
in a Simulink Model and Passing
Them to a Black Box
Describes how to access generics/parameters from
the masked counter and pass them onto the black box
to override the default local parameters in the VHDL
file.