User guide

32 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 1: Hardware Design Using System Generator
This design is comprised of six clock rates – 1, 2, 4, 8, 20, 40 with respect to the 10 ns
global clock constraint. The timing report validates the correct clock generation and
propagation by System Generator as follows:
♦ DCM-based clocks: clk_1 (CLK0 ->10 ns), clk_2 (CLKFX ->20 ns) , clk_4 (CLKDIV
->40 ns) generated by the DCM based on the 10 ns global clock input
♦ Clock Enable-based clocks: ce_8 (80 ns), ce_20 (200 ns), ce_40 (400 ns) generated
by clock enables based on the clk_4 clock input
Next you want to perform a behavior simulation using the ModelSim.
9. As shown in the following figure, move to the Sources for dialog box in the Sources
window, then select Behavioral Simulation
Note:
System Generator automatically creates the top-wrapper VHDL testbench, script file and
input/output stimulus data files. The Processes tab changes and displays according to the
Sources type being selected.
10. Simulate the design, as shown above, by double-click on Simulate Behavioral Model
in the Processes window
1. Select
2. Double Click