User guide

316 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 3: Using Hardware Co-Simulation
Manual Specification of Board-Specific Ports
You can manually specify your own board-specific ports when creating a board support
package. To define board-specific ports for your FPGA board, you must do the following:
• Add all board-specific ports to the yourboard.ucf template file. Each constraint
should be accompanied by a special comment, <port> contingent, where <port>
is the name of the board specific port. When System Generator compiles a model for
hardware, it creates a custom UCF file. Constraints associated with signals that aren't
used in the model are removed from the custom UCF file.
Example constraints for ports adc1_d(0) and adc1_d(1):
net adc1_d(0) loc = af20; # adc1_d contingent
net adc1_d(1) loc = ad18; # adc1_d contingent
• Declare all board-specific ports in the yourboard_postgeneration.m function.
Note:
Bi-directional ports are currently not supported.
Include this line in yourboard_postgeneration.m function:
params.('non_memory_mapped_ports') = non_mm_ports;
• Customize a gateway with the board-specific port information:
♦ Create a library and add a gateway
♦ Name the Gateway with the name of your board specific port (this name must
match the port name used in the post-generation function and UCF file)
♦ Select the Gateway by clicking on it
♦ In the MATLAB command window, type the following
> xlSetNonMemMap(gcb, 'Xilinx', 'jtaghwcosim')
♦ Save the library
You are now ready to use your board-specific gateway in System Generator. When you
include the gateway in your model, you must make sure the signals that drive (or are
driven by) the gateway have widths that match the widths of the ports in hardware. You
can force the width of a signal driving a gateway out by preceding it with a convert block.