User guide

System Generator for DSP User Guide www.xilinx.com 31
UG640 (v 12.2) July 23, 2010
System-Level Modeling in System Generator
a. Double-click on the file hybrid_dcm_ce_case1_dcm_mcw.vhd, then scroll
down to view the DCM component declaration as shown below by the VHDL
code snippet:
b. Observe that System Generator automatically infers and instantiates the DCM
instance and its parameters according to the required clock outputs.
c. Close the VHDL file.
Next, you are going to examine the clock propagation by examining the ISE timing report.
First, you must generate the report.
7. Open the following folder: Processes view > Implement Design > Place & Route >
Generate Post-Place & Route Static Timing
8. Double -click on Analyze Post-Place & Route Static Timing and you should see the
information in the figure below: