User guide

298 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 3: Using Hardware Co-Simulation
c. If the LCD display does not show the information correctly, press the System
ACE™ Reset button to reconfigure the FPGA.
11. Verify the Ethernet Interface and Connection Status
a. To ensure the board is reachable by the host, issue ICMP ping from the host to
check the connectivity. For example, type "ping 192.168.8.1" on a console to test the
connectivity to a board with IP address 192.168.8.1.
b. The target FPGA listens on the UDP port 9999. Please ensure the underlying
network does not block the associated traffic when network-based Ethernet
configuration is used. This does not affect point-to-point Ethernet configuration.
For in-depth reference information on the Spartan-3A 3400A Development Board, please
refer to the following online manual:
http://www.xilinx.com/support/documentation/boards_and_kits/ug498_s3a_3400_bo
ard.pdf