User guide

System Generator for DSP User Guide www.xilinx.com 275
UG640 (v 12.2) July 23, 2010
Real-Time Signal Processing using Hardware Co-Simulation
For high-speed processing applications, the hardware co-simulation block should be
configured to operate in Free Running clock mode. When this mode is used, the
synchronization between the FPGA and Simulink are handled entirely by the lockable
shared memories. By running the FPGA in free-running mode, you allow it to run fast
enough to process a complete video frame in a single Simulink cycle. Keep in mind that the
hardware co-simulation block circuitry waits to acquire lock before processing data. Since
the lock cannot be granted until the hardware co-simulation block is woken up, the FPGA
sits idle until new data is presented in the input buffer.
12. Double-click on the hardware co-simulation block and choose a Free Running
Clock under the Basic Tab.
You are now ready to simulate the design.
13. Press the Simulink Start button to start simulation.
Two windows will appear showing the original and filtered video streams.
The left image is the original video frame. The image on the right is the same frame that has
been processed using the "smooth" filter kernel. Note that the smoothing filter is just one of
several filters that can be applied to the video source.