User guide

System Generator for DSP User Guide www.xilinx.com 273
UG640 (v 12.2) July 23, 2010
Real-Time Signal Processing using Hardware Co-Simulation
lock of Foo and Bar, causing the FPGA shared memory images to be transferred
back to the host PC.
c. The Shared Memory Read block wakes up and requests lock of the output buffer
lockable shared memory Bar. The block reads a video from the output buffer and
drives its output port with the processed video frame data.
Note that the three steps listed above assume a specific sequencing of the hardware co-
simulation and Shared Memory Read and Write blocks. To ensure these blocks are
properly sequenced, you can set block priorities, where a lower priority block is woken up
first during simulation.