User guide

System Generator for DSP User Guide www.xilinx.com 269
UG640 (v 12.2) July 23, 2010
Real-Time Signal Processing using Hardware Co-Simulation
Note: The output buffer shared memory does not release lock until the output buffer is full. To avoid
deadlock, the number of valid assertions by the data path should equal the output memory buffer size
for a given processing cycle.
Applying a 5x5 Filter Kernel Data Path
You will now apply a data path to the I/O buffering interface to demonstrate a complete
system capable of processing a 128x128 8-bit grayscale video stream in real-time. You have
chosen to use a 5x5 image processing kernel to implement the data path portion of the
high-speed buffering interface. For more information about the filter kernel, refer to the
System Generator demo entitled sysgenConv5x5. You begin by considering various
aspects of the design implementation.
3. From the MATLAB console, change directory to
$SYSGEN/examples/shared_memory/hardware_cosim/conv5x5_video.
4. Open conv5x5_video_ex.mdl from the MATLAB console.
Buffer and Data Path Configuration
With the frame and pixel constraints in mind, the input and output buffer parameter
dialog boxes are configured with a depth of 128x128 (16K) words and a word width of 8-
bits. This depth allows the interface to process a complete frame in a single simulation
cycle. Note that these configuration parameters are propagated automatically to the
lockable shared memories that implement the buffer storage.
The data path uses line buffers to properly align data samples in the filter kernel. The size
of these line buffers can be parameterized to accommodate different frame sizes. In this
example, the line buffers are implemented in the Virtex2 5 Line Buffer block in the
conv5x5_video_ex/5x5_filter subsystem, and are pre-configured with a line size of