User guide

262 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 3: Using Hardware Co-Simulation
15. Record the amount of time required to simulate the design for 10000 cycles.
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16. Close the design, but leave the hardware co-simulation library open since you will
need it in the next topic.
In the simulation above, hardware co-simulation uses single word transfers. That is,
whenever there is a new simulation value to be read or written to the hardware co-
simulation, the PC initiates a transaction with the FPGA. The next topic describes how
vector transfers may be used to increase simulation speed by making more efficient use of
the available hardware co-simulation bandwidth.
Using Vector Transfers
The System Generate Shared Memory Read and Write blocks allow you to use vector
transfers with hardware co-simulation. These blocks may be found in the Shared Memory
library in the Xilinx Blockset.
The Shared Memory Write block accepts a Simulink scalar, vector, matrix or frame data
type and writes the data sequentially into a shared memory. The complete contents of the
Simulink signal are written into the shared memory in a single simulation cycle. As is the
case with all shared memory blocks, an association is made between a Shared Memory
Read or Write block and another shared memory by specifying the same shared memory
name.
Matrix types are treated as having a column-major order. That is, when data is written
sequentially into a shared memory, the elements in a column are written first before
advancing to the next column. For example, assume you have the matrix of data shown
below. During simulation, this matrix data is written into the FIFO (or shared memory) in
the following order:
Using these blocks, it is possible to read or write full vector, frame, or matrix signals into
shared memories, provided the following conditions are met:
• The input signal driven to a shared memory write block is an 8-bit, 16-bit, or 32-bit
signed or unsigned integer;
• The number of elements in the vector or matrix does not exceed the depth of the
shared memory or FIFO.
• The data width of the Shared Memory Read or Write block (i.e., the bitwidth of the
scalar, or vector or matrix element) equals the shared memory or FIFO data width.
You can use these blocks in the example design to read and write vectors of data samples
to the MAC filter in a single software / hardware transaction.