User guide

System Generator for DSP User Guide www.xilinx.com 259
UG640 (v 12.2) July 23, 2010
Frame-Based Acceleration using Hardware Co-Simulation
Generator cores, the actual depth of the hardware FIFO is n-1 words, where n is the depth
specified on the dialog box.
You will now have a chance to simulate the design to see how fast it runs in software.
3. Press the Simulink Start button to simulate the design in software.
4. Record the time required to simulate the design for 10000 cycles. To get an accurate
measurement, it is preferable to leave the scope block closed since the graphic updates
may affect simulation performance.
You may adjust the Slider Gain bar during simulation to see how the presence of additional
noise affects the filter performance. You may view the filtered and unfiltered data in the
output scope block. The top axis shows the unfiltered input data. The bottom axis shows
the filtered data results.