User guide

System Generator for DSP User Guide www.xilinx.com 255
UG640 (v 12.2) July 23, 2010
Frame-Based Acceleration using Hardware Co-Simulation
buffers is limited by the amount of internal memory available on the target device. In
System Generator, shared memory blocks provide interfaces that implement such buffers.
A question that quickly comes to mind is why not use standard FIFO or memory blocks?
The buffers required for hardware co-simulation differ from traditional FIFOs and
memories in that they must be controllable by both the PC and FPGA user design logic.
The standard FIFO and memory blocks provided by System Generator can only interface
with user design logic.
There are two types of shared memories that provide this control: lockable shared
memories and shared FIFOs. These blocks provide different buffering styles; each with
their own handshaking protocols that determine when and how burst transactions with
the FPGA occur. In this tutorial, primary attention is focused on shared FIFO buffers. For
an example on how to use lockable shared memories, please refer to the tutorial entitled
Real-Time Signal Processing using Hardware Co-Simulation. You may find the lockable
shared memory and FIFO blocks in the Shared Memory library of the Xilinx Blockset.
Because shared FIFOs play a central role in enabling vector transfers, it is worth a brief
aside to discuss their behavior. A shared FIFO pair is comprised of a To FIFO block and a
From FIFO block that specify the same name (e.g., Bar in the figure above). The To FIFO
block provides the "write side" control signals, while the From FIFO block provides the
"read side" control signals. When used together, a shared FIFO pair is conceptually the
same thing as a single FIFO – only the control signals for the two sides are graphically
disjoint. This means that a shared FIFO pair shares the same FIFO memory space. For
example, if you write data into a To FIFO block, you may retrieve the same data by reading
from the From FIFO block. The connection between these two blocks is implicit; shared
FIFOs are associated with one another by name and not by explicit Simulink wires.
Shared FIFOs and shared memories in general may be compiled for hardware co-
simulation. Note that although this tutorial touches briefly on how shared FIFOs are co-
simulated, it is useful to refer to the topic titled Co-Simulating Shared FIFOs for more in-
depth information. When one-half of a shared FIFO block is compiled for hardware co-
simulation, a full FIFO block is embedded in the FPGA using the FIFO Generator core. One
side of the FIFO connects to user design logic (i.e., the System Generator logic that
connected to the shared FIFO block). The other half connects to interface logic that allows
it to be controlled by the PC. This side of the FIFO may be controlled by other System
Generator software model logic (e.g., the half of the shared FIFO), by a C program or
software executable, or by a MATLAB program. By compiling shared FIFOs for hardware