User guide

System Generator for DSP User Guide www.xilinx.com 249

UG640 (v 12.2) July 23, 2010

Shared Memory Support

is possible for the PC to write to the register using System Generator's hardware co-

simulation interfaces.

When a To Register block is compiled for hardware co-simulation, as shown in the figure

below, the input ports are wired to user logic while the output port is wired to PC interface

logic. You may access a shared register during hardware co-simulation using the other half

of the shared register (i.e., using a To or From Register block), a C program or executable

(System Generator API), or a MATLAB program.

For designs that use hardware co-simulation, shared register pairs are typically distributed

between software and FPGA hardware. In other words, one half of the pair is implemented

in the FPGA while the other half is simulated in software using a To or From Register

block. When data is written to a software To Register block, the hardware register is

updated to with the same data. Similarly, when data is written into the hardware register,

the same data is read by the From Register software block. A software shared register may

connect to a hardware shared register simply by specifying the name of the shared register

as it was compiled for hardware co-simulation.

Note:

You may find the names of all shared memories embedded inside an FPGA co-simulation

design by viewing the Shared Memories tab on a hardware co-simulation block.

When a software / hardware shared memory pair is co-simulated, System Generator

transparently manages the interaction between the PC and FPGA hardware. This means

that a shared register pair simulated in software should behave the same as a shared

Co-Simulating Shared FIFOs

A To FIFO, From FIFO or shared FIFO pair may be generated and co-simulated in hardware.

Here and throughout this topic, a shared FIFO pair is defined as a To FIFO block and From

FIFO block that specify the same name (e.g., 'Bar'). In hardware, a shared FIFO is

implemented using the FIFO Generator core. The core is configured to use independent

(asynchronous) clocks, and block memory for data storage. This topic explains why co-

simulating shared FIFOs is useful, and also how these blocks behave in hardware.