User guide

System Generator for DSP User Guide www.xilinx.com 243
UG640 (v 12.2) July 23, 2010
Shared Memory Support
Compiling Shared Memories for Hardware Co-Simulation
System Generator allows shared memory and shared memory derivative (e.g., shared
FIFO and shared register) blocks to be compiled for hardware co-simulation. Designs that
include shared memories are compiled for hardware co-simulation the same way
traditional System Generator designs are compiled – by selecting a compilation target and
pressing the Generate button on the System Generator dialog box. A design containing
shared memory blocks may be compiled for hardware co-simulation provided the
requirements described in the topic Restrictions on Shared Memories are satisfied.
When a shared memory is compiled for hardware co-simulation, it is implemented in
hardware either by a core or HDL component. The table below shows how shared memory
blocks are mapped to hardware implementations
There are two ways in which shared memories are compiled for hardware co-simulation.
The type of compilation depends on whether the shared memory name is unique in the
design, or if the shared memory has a partner who shares the same name. The following
topics describe the two types of compilation behavior.
Single Shared Memory Compilation
A shared memory block is considered "single" if it has a unique name within a design.
When a single shared memory is compiled for hardware co-simulation, System Generator
builds the other half of the memory and automatically wires it into the resulting netlist.
Additional interfacing logic is attached to the memory that allows it to communicate with
the PC. When you co-simulate the shared memory, one half of the memory is used by the
logic in your System Generator design. The other half communicates with the PC
interfacing logic as shown in the figure below. In this manner, it is possible to communicate
with the shared memory embedded inside the FPGA while a simulation is running.
The shared memory hardware and interface logic are completely encapsulated by the
hardware co-simulation block that is generated for the design. By co-simulating a
hardware co-simulation block that contains a shared memory, it is possible for your design
logic and host PC software to share a common address space on the FPGA.
To Block From Block Hardware Implementation
Shared Memory Shared Memory Dual Port Block Memory
To FIFO To FIFO Fifo Generator
To Register To Register synth_reg_w_init.(vhd,v)