User guide

228 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 3: Using Hardware Co-Simulation
Note: A status dialog box (shown below) will appear after you press the Generate button. During
compilation, the status box provides a Cancel and Show Details button. Pressing the Cancel button
will stop compilation. Pressing the Show Details button exposes details about each phase of
compilation as it is run. It is possible to hide the compilation details by pressing the Hide Details
button on the status dialog box.
The configuration bitstream contains the hardware associated with your model, and also
contains additional interfacing logic that allows System Generator to communicate with
your design using a physical interface between the board and the PC. This logic includes a
memory map interface over which System Generator can read and write values to the
input and output ports on your design. It also includes any board-specific circuitry (e.g.,
DCMs, external component wiring) that is required for the target FPGA board to function
correctly.
Hardware Co-Simulation Blocks
System Generator automatically creates a new hardware co-simulation block once it has
finished compiling your design into an FPGA bitstream. A Simulink library is also created
in order to store the hardware co-simulation block. At this point, you can copy the block