User guide

System Generator for DSP User Guide www.xilinx.com 201
UG640 (v 12.2) July 23, 2010
Designing with Embedded Processors and Microcontrollers
The following are some of benefits of using Co-Debug between System Generator and
SDK:
• Concurrent visibility of software and hardware for debug
♦ Set a breakpoint and debug while the MicroBlaze and hardware are stopped
♦ Signals to probe do not need to be chosen before the bit stream is generated
• Find a bug, modify the C code, recompile and update the bitstream in seconds.
♦ No need to rerun synthesis and the implementation flow when the software
changes
♦ The initial software program (ELF file) is automatically updated to the download
bitstream. You no longer need to manually click the Compile and update
bitstream button on the Hardware Co-Simulation block.
• Tight integration
♦ The SDK project is automatically setup with the correct hardware platform
♦ The required logic is automatically added to the design
Objectives
After completing this tutorial exercise, you will be able to:
• Use shared memories in System Generator to interface DSP hardware with the
MicroBlaze embedded processor
• In XPS, create a basic XPS project using the BSB Wizard
• In System Generator, import an XPS project into a Sysgen design
• In System Generator, generate a hardware co-simulation block and launch SDK
directly from System Generator
• In SDK, co-debug a design by single-stepping and observing output waveforms on a
Simulink scope
Tutorial Exercise Setup
The following software is required to be installed on your system to successfully complete
this exercise:
• Xilinx ISE Design Suite 12.1 (System Edition)
• MATLAB / Simulink R2009a or R2009b
• SP601 Platform
• JTAG Cables that come with the SP601 Platform