User guide

System Generator for DSP User Guide www.xilinx.com 17
UG640 (v 12.2) July 23, 2010
A Brief Introduction to FPGAs
division multiplexed (TDM) data streams. The addressable shift register (ASR) block,
with a function depicted in the figure below, provides an arbitrary width, arbitrary depth
tapped delay line. This block is of particular interest to the DSP engineer, since it can be
used to implement tapped delay lines as well as sweeping through TDM data streams.
Although random access memories can be constructed either out of the BRAM or LUT
(RAM16x1) primitives, doing so can require considerable care to ensure most efficient
mappings, and considerable clerical attention to detail to correctly assemble the primitives
into larger structures. System Generator removes the need for such tasks.
For example, the dual port RAM (DPRAM) block shown in the figure below maps
efficiently onto as many BRAM or RAM16x1 components on the device as are necessary to
implement the desired memory. As can be seen from the mask dialog box for the DPRAM,
the interface allows you to specify a type of memory (BRAM or RAM16x1), depth (data
width is inferred from the Simulink signal driving a particular input port), initial memory
contents, and other characteristics.
In general, System Generator maps abstractions onto device primitives efficiently, freeing
you from worrying about interconnections between the primitives. System Generator
employs libraries of intellectual property (IP) when appropriate to provide efficient
implementations of functions in the block libraries. In this way, you don’t always have to