User guide

System Generator for DSP User Guide www.xilinx.com 165
UG640 (v 12.2) July 23, 2010
EDK Support
Exposing Processor Ports to System Generator
The preferred mechanism for getting data to and from the processor and System Generator
is via shared-memories. It is however possible to expose ports on the top-level of the
processor to System Generator.
The top-right box in the figure above shows a snippet from an EDK project in XPS. The
external port list has among other ports, a user-defined port called myExternalPort.
After importing the EDK project, open up the processor's block GUI in System Generator.
Select the Advanced tab to reveal the processor port interface table.
The port list shows all the top-level ports available on the processor. This port list has been
filtered to remove clock ports and also signals used by System Generator to implement the
memory-map interface. In this example, the RS232 ports, sys_rst_pin and myexternalport are
shown to be ports that can be exposed to the top-level of the System Generator block.
Selecting the expose check box will cause the port to be exposed on the EDK Processor
block. As shown in the figure above, the display name of the port can be changed, should
the original name be too long.
This mechanism allows ports from the processor to be directly exposed to the System
Generator design without going through the memory map generated by System
Generator. You may choose to do this to expose the reset ports on the processor, or to
expose interrupt ports directly to the System Generator diagram.