User guide

162 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 2: Hardware/Software Co-Design
Starter board). You have to remove the JTAG-Based MDM (Microprocessor Debug
Module) peripheral from the imported XPS project. Otherwise, you need to switch to
the Point-to-Point Ethernet-Based Hardware Co-Simulation flow and use the Ethernet
for downloading the bitstream.
• Constraint handling: The EDK Processor block automatically modifies the UCF (user
constraint file) file from the imported XPS based on the compilation flow that is used.
Upon importing an XPS project, a copy of the modified UCF file is placed under
<xps_project_dir>/data/sg_<xps_project_name>.ucf. The snippet of a modified
UCF file is shown below. Constraints that belong to certain external ports of the
imported XPS are commented/uncommented depending on whether or not the port
is exposed on the EDK Processor block. The input clock ports are commented out in
the hardware co-simulation flow automatically.
# constraints for pin 'fpga_0_RS232_Uart_1_RX_pin' (not exposed)
Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15 | IOSTANDARD=LVCMOS33;
# constraints for pin 'fpga_0_RS232_Uart_1_TX_pin' (not exposed)
Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20 | IOSTANDARD=LVCMOS33;
# constraints for pin 'fpga_0_clk_1_sys_clk_pin' (exposed, clock port)
# Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
# TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
# Net fpga_0_clk_1_sys_clk_pin LOC = AH15 | IOSTANDARD=LVCMOS33;
In case where you do not want the EDK Processor block to make automatic
modifications, you can put the line #### SYSGEN VERBATIM ### in the original XPS
project UCF file. All the lines after this commented line will be untouched. See the
explanation found from the beginning of the modified UCF file, which is also shown in
the code snippet below.
# This file is generated automatically by System Generator for DSP from
# the following file:
#
# C:\dev\trunk\test\edk\edkplbimport\EDKPrj\data\system.ucf
# Do NOT modify this file directly. Instead, change the above original
# file. Synchronize the processor memory map, or re-import the XPS
# project to apply the changes. # # In case that the automatic changes
by System Generator for DSP are
# undesired, put the following comment in the above original file. All
# the contents after this comment will be copied verbatim.
# #### SYSGEN VERBATIM ###