User guide

160 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 2: Hardware/Software Co-Design
PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK,
CLK_FREQ = 100000000
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 125000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 4.00.a
PORT CLKIN = dcm_clk_s # input clock
PORT CLKOUT0 = clk_125_0000MHz # output clock
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END
2. Next, you should simply comment out the clock generator. The output clock is directly
attached to the board input clock. The modified
system.mhs file is like the following:
PORT fpga_0_clk_1_sys_clk_pin = clk_125_0000MHz, DIR = I, SIGIS = CLK,
CLK_FREQ = 100000000
# BEGIN clock_generator
# PARAMETER INSTANCE = clock_generator_0
# PARAMETER C_CLKIN_FREQ = 100000000
# PARAMETER C_CLKOUT0_FREQ = 125000000
# PARAMETER C_CLKOUT0_PHASE = 0
# PARAMETER C_CLKOUT0_GROUP = NONE
# PARAMETER C_CLKOUT0_BUF = TRUE
# PARAMETER C_EXT_RESET_HIGH = 0
# PARAMETER HW_VER = 4.00.a
# PORT CLKIN = dcm_clk_s # input clock
# PORT CLKOUT0 = clk_125_0000MHz # output clock
# PORT RST = sys_rst_s
# PORT LOCKED = Dcm_all_locked
# END
3. The Dcm_all_locked pin on the clock generator is used to indicate whether the output
clock signal is locked with the input clock signal. Replace the input pins driven by this
signal with
net_vcc. These kind of changes can be tricky in some design scenarios. So
far, no abnormality has been observed for the hardware peripherals generated from
BSB.
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 2.00.a
PORT Slowest_sync_clk = clk_125_0000MHz
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = net_vcc # changed from Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END