User guide

System Generator for DSP User Guide www.xilinx.com 15
UG640 (v 12.2) July 23, 2010
A Brief Introduction to FPGAs
MHz are common today) and a highly-distributed memory architecture gives the system
designer an ability to exploit parallelism in DSP (and other) applications that operate on
data streams. For example, the raw memory bandwidth of a large FPGA running at a clock
rate of 150 MHz can be hundreds of terabytes per second.
There are many DSP applications (e.g., digital up/down converters) that can be
implemented only in custom integrated circuits (ICs) or in an FPGA; a von Neumann
processor lacks both the compute capability and the memory bandwidth required.
Advantages of using an FPGA include significantly lower non-recurring engineering costs
than those associated with a custom IC (FPGAs are commercial off-the-shelf devices),
shorter time to market, and the configurability of an FPGA, which allows a design to be
modified, even after deployment in an end application.
When working in System Generator, it is important to keep in mind that an FPGA has
many degrees of freedom in implementing signal processing functions. You have, for
example, the freedom to define data path widths throughout your system and to employ
many individual data processors (e.g., multiply-accumulate engines), depending on
system requirements. System Generator provides abstractions that allow you to design for
an FPGA largely by thinking about the algorithm you want to implement. However, the
more you know about the underlying FPGA, the more likely you are to exploit the unique
capabilities an FPGA provides in achieving high performance.
The remainder of this topic is a brief introduction to some of the logic resources available in
the FPGA, so that you gain some appreciation for the abstractions provided in System
Generator.
The figure above shows a physical view of a Virtex®-4 FPGA. To a signal DSP engineer, an
FPGA can be thought of as a 2-D array of logic slices striped with columns of hard macro
blocks (block memory and arithmetic blocks) suitable for implementing DSP functions,
embedded within a configurable interconnect mesh. In a Virtex®-4 FPGA, the DSP blocks
(shown in the next figure) can run in excess of 450 MHz, and are pitch-matched to dual
port memory blocks (BRAMs) whose ports can be configured to a wide range of word sizes
(18 Kb total per BRAM). The Virtex®-4 SX55 device contains 512 such DSP blocks and
BRAMs. In System Generator, you can access all of these resources through arithmetic and