User guide

128 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 1: Hardware Design Using System Generator
locked : out std_logic;
psdone : out std_logic;
status : out std_ulogic_vector(7 downto 0));
end component;
--------------------------------------
-- DCM Attributes
--------------------------------------
attribute dll_frequency_mode : string;
attribute duty_cycle_correction : string;
attribute startup_wait : string;
attribute clkdv_divide : string;
attribute clkfx_multiply : string;
attribute clkfx_divide : string;
attribute clkin_period : string;
attribute duty_cycle_correction of dcm0 : label is "true";
attribute startup_wait of dcm0 : label is "false";
attribute dll_frequency_mode of dcm0 : label is "low";
attribute clkdv_divide of dcm0 : label is "3";
attribute clkfx_multiply of dcm0 : label is "2";
attribute clkfx_divide of dcm0 : label is "1";
attribute clkin_period of dcm0 : label is "10";
signal clk0unbuf : std_logic;
signal clk0buf : std_logic;
signal clkfxbuf : std_logic;
signal clk2xunbuf : std_logic;
signal clkfxunbuf : std_logic;
signal clkdvunbuf : std_logic;
signal clkdvbuf : std_logic;
signal ff1,ff2,ff3,ff4 : std_logic;
signal dcm_rst : std_logic;
signal intlock : std_logic;
----------------------------------------------------------------------
---------
-- The top level instantiates the SysGen design, a DCM, and two BUFGs.
-- The DCM generates two clocks of different frequencies.
-- These two clocks are used to drive the two different clock domains
-- in the SysGen block.
----------------------------------------------------------------------
---------
begin
dcm0: dcm
-- synopsys translate_off
generic map (dll_frequency_mode => frequency_mode,
clkdv_divide => clkdv_divide_generic,
clkfx_multiply => clkfx_multiply_generic,
clkfx_divide => clkfx_divide_generic)
-- synopsys translate_on
port map (clkin => clk,
clkfb => clk0buf,
dssen => '0',
psincdec => '0',
psen => '0',
psclk => '0',
rst => dcm_rst,
clk0 => clk0unbuf,
clk2x => clk2xunbuf,