User guide

System Generator for DSP User Guide www.xilinx.com 127
UG640 (v 12.2) July 23, 2010
Generating Multiple Cycle-True Islands for Distinct Clocks
use unisim.vcomponents.all;
entity top_wrapper is
port (
clk : in std_logic;
din_a : in std_logic_vector(7 downto 0);
din_b : in std_logic_vector(7 downto 0);
dout_a : out std_logic_vector(7 downto 0);
dout_b : out std_logic_vector(7 downto 0)
);
end top_wrapper;
architecture structural of top_wrapper is
--------------------------------------
-- SysGen Model Component Declaration
--------------------------------------
component two_async_clks
port (
din_a: in std_logic_vector(7 downto 0);
din_b: in std_logic_vector(7 downto 0);
ss_clk_domaina_cw_ce: in std_logic := '1';
ss_clk_domaina_cw_clk: in std_logic;
ss_clk_domainb_cw_ce: in std_logic := '1';
ss_clk_domainb_cw_clk: in std_logic;
dout_a: out std_logic_vector(7 downto 0);
dout_b: out std_logic_vector(7 downto 0)
);
end component;
component bufg
port(i: in std_logic;
o: out std_logic);
end component;
--------------------------------------
-- DCM Component Declaration
--------------------------------------
component dcm
-- synopsys translate_off
generic (clkout_phase_shift : string := "fixed";
dll_frequency_mode : string := "low";
duty_cycle_correction : boolean := true;
clkdv_divide : real := 3;
clkfx_multiply : integer := 2;
clkfx_divide : integer := 1);
-- synopsys translate_on
port (clkin : in std_logic;
clkfb : in std_logic;
dssen : in std_logic;
psincdec : in std_logic;
psen : in std_logic;
psclk : in std_logic;
rst : in std_logic;
clk0 : out std_logic;
clk90 : out std_logic;
clk180 : out std_logic;
clk270 : out std_logic;
clk2x : out std_logic;
clk2x180 : out std_logic;
clkdv : out std_logic;
clkfx : out std_logic;
clkfx180 : out std_logic;