User guide

System Generator for DSP User Guide www.xilinx.com 115
UG640 (v 12.2) July 23, 2010
Using FDATool in Digital Filter Applications
Run the Simulation
1. Change the simulation time to 0.05, then run the simulation
You should get the message shown in the figure below.
System Generator gets its input sample period from the din Gateway In block which
has 1/Fs specified as the data input sample period. As the MAC-based FIR filter is
over-sampled according to the number of taps, the System Clock Period will always be
equal to 1/(Filter Taps * Fs).
2. Double click on the System Generator token and change the Simulink system period to
specify the System Clock Period as 5.273427e-007 = 1/(43 * 44100) as shown below.
3. Run the simulation again and notice that the Xilinx implementation of the MAC-based
FIR filter meets the original filter specifications and that its frequency response is
almost identical to the double precision Simulink models.
As you can see, the filter passband response measurement as well as zeros can clearly
be seen. You should get similar frequency responses as shown in the following figure.