User guide

108 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 1: Hardware Design Using System Generator
Clock Enable Planning
When using the Clock Enables clocking option, the clock enables are often the limiting
path at high frequencies. This is partially due to System Generator's use of LUTs to gate
clocks at the destination. To avoid clock enables in the critical path, avoid using the System
Generator upsampled and downsampled clock domains. This requires the manual use of
clock enables for logic that runs at less than the system clock rate.
Place and Route Flow
• Use the command map -timing with effort level high for both map and place
• Use trce –v 100 to get a good sense of the failing nets and inspect the
xflow/design.twr file to understand the nature of the design's timing.
• The file bitstream_v4.opt is available in the examples/dsp48 directory. This
file can be used with the Bitstream compile target to set the PAR options mentioned
above.
Synthesis Flow
• Use Synplify Pro with retiming and pipelining enabled to avoid having to manually
pipeline every LUT and signal.
• Use Synplify Pro with the fanout limit set around 32 to avoid long net delays.
• Open compiled projects in Synplify Pro and inspect the generated logic using the
RTL- and Gate-level views to get a good idea of what logic is being generated.
• The file syn.pl is available in the examples/dsp48 directory. Place this file in
<ISE_Design_Suite_tree>/sysgen/scripts directory to modify the synthesis
options in System Generator
Logic Depth Planning
The following rules seem to allow the LUT fabric to run at 450 MHz using a -11 V4 device:
• Only one net can be allowed in a critical path at 450 MHz. This allows a 4:1 mux to a
reg a 4_input LUT to a reg or a net through a LUT directly to a DSP48
• Counters up to 16-bits can be used, but do not use count limited counters without
additional pipelining
• If accumulators or counters are used, invert the enable line to an active-low condition
to prevent a extra LUT from being inserted in the critical path
• Any adders must have local input registers. It may be necessary to place control
counters in the DSP48 to insure speed.
Fanout Planning
Avoid fanouts of more than 32 LUTs or 8 DSP48s or BRAMs. This can be avoided by
inserting additional pipeline registers in these signals paths.
Register Retiming
Check retiming on delay blocks to allow them to be used as registers for pipelining. Then
use Synplify Pro or XST with retiming enabled to allow the synthesis tool to move registers
into optimal positions.