User guide

System Generator for DSP User Guide www.xilinx.com 107
UG640 (v 12.2) July 23, 2010
Design Styles for the DSP48
8. Use RAMs, SRL16 to clock out control patterns instead of state machines
9. Use DSP48 to implement counters and adders greater than 8-16 bits
10. Use area constraints – "INST ff1* LOC = SLICE_X0Y8:SLICE_X1Y23;"
Physical Planning for DSP48-Based Designs
The DSP48 requires correct placement to achieve dense, high performance designs. While
the automatic place and route tools do a good job, the best results may require manual
placement of DSP48 and RAM blocks. There are several additional issues with the DSP48s.
Cascade Routing Buses
Adjacent DSP48 blocks are connected with two local buses called PCOUT, and BCOUT.
The PCOUT bus is used to pass accumulation data from one DSP48 to the next. The
BCOUT bus is used to pass delayed B input data to the next DSP48. The DSP48 and DSP48
Macro block both support PCOUT and BCOUT buses. The use of the buses is shown in the
figure above, which illustrates a pipelined 4-Tap Type 1 FIR filter.
C-Input Sharing
Each pair of DSP48s share a single C input. You should be aware of this when you do
resource planning. Since the placer will not always find the most optimal placement to
share C inputs, DSP48s should avoid using C inputs if possible.
Adder Trees Planning
Tree-based filter topologies are problematic for efficient DSP48 implementation. An adder
tree requires isolated 2-input adders. Two input 36-bit adders can be implemented using a
single DSP48, however this requires a C input and precludes the use of the multiplier. In
addition, the long signals between DSP48s may require additional pipeline stages. A better
approach is to convert the tree into a pipelined cascade.
Placement
Most designs will benefit from some placement of DSP48 and BRAMs. Use of area
constraints to constrain LUT fabric logic placement may also be beneficial.
Signal Length Planning
At 500 MHz, signal lengths should be limited to around 20 slices. This means that long
signals should have multiple pipeline stages.