User guide

100 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 1: Hardware Design Using System Generator
Designs Using Standard Components
Designs for Xilinx FPGAs such as Spartan®-3 will compile to the Virtex®-4 devices.
Multipliers will be mapped into the DSP48 block, however, logic synthesis tools cannot
pack adders and muxes into the DSP48 block since these blocks are delivered as cores
which prevents synthesis from optimizing the logic. Place and route tools do place the
MULT18x18S and MULT18x18 into the DSP48 block but do not pack the adder, or mux into
the DSP48 block. (PAR will however pack the mux into the LUT-based adder).
To obtain the best possible performance, you should set the multiplier latency to 3 and
include an input register to cover the delay from the DSP48's output to the adder. In
Virtex®-4, unlike Spartan®-3 devices, the multiply speed in nearly independent of bit
width. For medium speed designs, this approach works fine.
An additional way to use the DSP48 is to use IP blocks optimized for the DSP48 such as the
MACFIR block available from coregen, or to use the architecture wizard to generate a
custom configured DSP48. Both of these approached require importing the logic
containing the DSP48 as a black box into System Generator. Simulation will require
ModelSim HDL cosim.
Designs Using Synthesizable Mult, Mux and AddSub Blocks
Synthesis tools now have the ability to infer DSP48 logic. This enables the tools to pack
adders, multipliers and muxes into the DSP48 block, as well as to enable the application of
retiming and other synthesis techniques such as register duplication.
If the design is composed of synthesizable blocks, both Synplify Pro and XST have
demonstrated the ability to infer DSP48s and to make use of the DSP48's local interconnect
buses (PCOUT-PCIN and BCOUT-BCIN). In the above example, three blocks have been
built using the MCode blocks which are defined by the following M-functions.
function o = xlsynmux2(i0,i1,sel)
if (sel==0) o=i0; else o=i1; end
function p = xlsynmult(a,b)
p=a*b;
function s = xlsynadd(a,b)
s=a+b;