User`s guide
Table Of Contents
- Preface
- Quick Start
- LTI Models
- Introduction
- Creating LTI Models
- LTI Properties
- Model Conversion
- Time Delays
- Simulink Block for LTI Systems
- References
- Operations on LTI Models
- Arrays of LTI Models
- Model Analysis Tools
- The LTI Viewer
- Introduction
- Getting Started Using the LTI Viewer: An Example
- The LTI Viewer Menus
- The Right-Click Menus
- The LTI Viewer Tools Menu
- Simulink LTI Viewer
- Control Design Tools
- The Root Locus Design GUI
- Introduction
- A Servomechanism Example
- Controller Design Using the Root Locus Design GUI
- Additional Root Locus Design GUI Features
- References
- Design Case Studies
- Reliable Computations
- Reference
- Category Tables
- acker
- append
- augstate
- balreal
- bode
- c2d
- canon
- care
- chgunits
- connect
- covar
- ctrb
- ctrbf
- d2c
- d2d
- damp
- dare
- dcgain
- delay2z
- dlqr
- dlyap
- drmodel, drss
- dsort
- dss
- dssdata
- esort
- estim
- evalfr
- feedback
- filt
- frd
- frdata
- freqresp
- gensig
- get
- gram
- hasdelay
- impulse
- initial
- inv
- isct, isdt
- isempty
- isproper
- issiso
- kalman
- kalmd
- lft
- lqgreg
- lqr
- lqrd
- lqry
- lsim
- ltiview
- lyap
- margin
- minreal
- modred
- ndims
- ngrid
- nichols
- norm
- nyquist
- obsv
- obsvf
- ord2
- pade
- parallel
- place
- pole
- pzmap
- reg
- reshape
- rlocfind
- rlocus
- rltool
- rmodel, rss
- series
- set
- sgrid
- sigma
- size
- sminreal
- ss
- ss2ss
- ssbal
- ssdata
- stack
- step
- tf
- tfdata
- totaldelay
- zero
- zgrid
- zpk
- zpkdata
- Index

connect
11-37
c =
x1 x2 x3 x4
? 2.5 0 0 0
y1 0 -3.2897 2.4544 0
y2 0 -13.501 18.075 0
? 0 0 0 -1.4142
d =
uc u1 u2 ?
? 0 0 0 0
y1 0 -0.5476 -0.141 0
y2 0 -0.6459 0.2958 0
? 0 0 0 2
Continuous-time system.
Note that the ordering of the inputs and outputs is the same as the block
ordering you chose. Unnamed inputs o r o utputs are denoted by
?.
To derive the overall block diagram model from
sys, specify the
interconnections and t he external inputs and o utputs. You need to connect
outputs 1 and 4 into input 3 (
u2), and output 3 (y2) into input 4. The
interconnection matrix
Q is therefore
Q = [3 1 –4
4 3 0];
Note that the second row of Q has been padded with a trailing zero. The block
diagram has two external inputs
uc and u1 (inputs 1 and 2 of sys), and two
external outputs
y1 and y2 (outputs 2 and 3 of sys). Accordingly, set inputs
and outputs as follows.
inputs = [1 2];
outputs = [2 3];